1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
A typical integrated circuit has several vertically stacked levels, with any given level comprising one or more layers of materials. The topmost level in an integrated circuit is referred to as a xe2x80x9cpassivation level.xe2x80x9d The passivation level helps protect an integrated circuit""s structures during packaging and in operation. Below the passivation level are metal and dielectric levels. Metal levels include metal lines for carrying electrical signals. Dielectric levels provide electrical isolation between metal levels.
The speed at which a signal is propagated in an integrated circuit is limited by the delay through the metal line carrying the signal. This delay, commonly known as xe2x80x9cRC delay,xe2x80x9d is determined by the product of the resistance (R) and capacitance (C) of the metal line. Reducing the resistance and/or capacitance of a metal line lowers its RC delay and increases signal propagation speed. Thus, reducing the RC delay of metal lines plays a major role in making integrated circuits run faster.
In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line""s resistance and resulting RC delay.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.